Application Specific Integrated Circuits (ASICs) are designed using a variety of Computer Aided Design (CAD) tools. The development of ASICs with CAD tools is often referred to as Electronic Design Automation (EDA).
An integrated circuit design can be represented at different levels of abstraction, such as the Register-Transfer level (RTL) and the logic level, using a hardware description language (HDL). VHDL and Verilog are examples of HDL languages. At any abstraction level, an integrated circuit design is specified using behavioral or structural descriptions or a mix of both.
The structural description of an integrated circuit is also referred to as a netlist. A netlist is a list of components and interconnections between the components. A netlist is hierarchical when any component in the netlist is itself a netlist.
At the logical level, the behavioral description is specified using boolean equations. The structural description is represented as a netlist of primitive cells. Examples of primitive cells are full-adders, NAND gates, latches, and D-Flip Flops.
At the RTL level, the behavioral description consists of program-like constructs, such as, variables, operators, conditionals, loops, procedures and functions. The structural description is a netlist of high-level macrocell components, such as adders, pipelined multipliers, ALUs, multiplexors, and register-files. This macrocell is also referred to as a datapath cell. Each macrocell or datapath cell has a corresponding netlist of primitive cells and a corresponding predesigned custom layout. This logic-level netlist of primitive cells, and the custom layout are generated using a silicon compiler tool. The timing and pin capacitance information of this logic-level netlist is required for analyzing the timing of a RTL level netlist.
A silicon compiler accepts as inputs a netlist composed of interconnected macrocells and produces as output a netlist composed of interconnected primitive cells, and a custom layout.
The functional relationships between several commonly used CAD tools is depicted in FIG. 1. One such CAD tool is an RTL Synthesizer 22. An RTL synthesizer 22 accepts as input an RTL description 24 of a design, written in an HDL language, such as VHDL or Verilog, and produces as output a netlist 26. The netlist 26 comprises a list of circuit components and the interconnections between the components. More particularly, the netlist 26 generated by the RTL synthesizer 22 is a hierarchical netlist composed of logic-level netlists (i.e., netlists of primitive cells) and RTL level netlists (i.e., netlists of datapath cells). The primitive cells, such as NAND gates, XOR gates and D-Flip-Flops, are obtained from a cell library 30. The area, timing and pin capacitance information of each primitive cell is also available from the cell library 30. The datapath cells, such as ALUs, adders and register files, are obtained by the RTL synthesizer 22 from a datapath library 38.
Other CAD tools may be used to verify that the circuit described in the netlist meets timing requirements or other constraints. For example, a logic synthesizer/timing analyzer 28 may be used to optimize the netlist for such purposes. When the netlist 26 is composed of logic-level netlists only, a logic synthesizer/timing analyzer 28 may analyze the timing of the netlist 26 using the timing constraints 32 and the timing and pin capacitance information of each primitive cell available from the cell library 30, and finally may produce an optimized netlist 36 with better timing performance than the original netlist 26.
The logic synthesizer/timing analyzer 28 may perform spatial optimization to decrease the area of a circuit defined by the netlist. The logic synthesizer/timing analyzer 28 may also operate to insure that the designed circuit meets a set of timing constraints 32. An integrated circuit may have specified timing constraints that define the maximum permissible time periods between receipt of a particular set of input signals and the generation of output signals on specified output nodes of the circuit. The timing performance of a circuit is a function of the delays through the logic gates of the circuit, wiring capacitances, input connector drive strengths, and output connector loads. The propagation times are computed by a timing analyzer built in the logic synthesizer/timing analyzer 28.
Prior art timing analyzers assess the timing performance of a circuit on the basis of a logic-level analysis. In other words, the timing analyzer determines timing performance by analyzing the primitive cells of the circuit; the timing analyzer does not directly determine the timing performance of the datapath cells (RTL components or macrocells), for which accurate timing information is not available in the datapath library 38. Based upon this logic-level analysis, the logic synthesizer/timing analyzer 28 modifies the logic-level netlist in order to insure that the circuit meets all specified constraints.
In these prior art methods, the circuit's netlist is modified at the logic-level only, but the RTL level netlist, if any, remains the same. Thus, prior art RTL synthesizers do not have accurate timing information for the RTL level netlist. In other words, datapath cell timing information is not available to the RTL synthesizer 22 when it is mapping the HDL description of a circuit to RTL components. Thus, prior art RTL synthesizers are unable to improve the timing performance of the RTL level circuit for a given timing constraint.
Since prior art timing analyzers rely upon logiclevel information, it is difficult to analyze the circuit design at the datapath cell level. Thus, it would be desirable to facilitate the analysis of a netlist composed of RTL and logic-level components. It would also be desirable to provide a method and apparatus for modifying a circuit at the RTL level. Such a capability would allow analyses of area and timing trade-offs that are not available with logic-level modifications. For example, at an RTL level, the architecture of a 64-bit adder can be easily changed from a ripple carry (slow and small) architecture to a carry look-ahead (fast and large) architecture to drastically improve the timing performance of critical paths.
After the logic synthesizer/timing analyzer 28 optimizes the netlist, there are a number of commercially available "silicon compilers", sometimes called "datapath compilers" or "place and route tools" 34, that may then be used to convert the optimized netlist 36 into a semiconductor circuit layout. The semiconductor circuit layout may then be used to manufacture the circuit.